The present invention relates generally to the manufacture of semiconductor devices and, more particularly, to a method of forming a double diffusion metal-oxide-semiconductor (DMOS) transistor to reduce processing complexity and improve the performance of the semiconductor devices.
FIG. 1A to FIG. 1E are cross-sections showing the manufacturing process of a DMOS transistor according to the prior art.
As shown in FIG. 1A, a gate oxide 12 is formed in the trench for gate and on the surface of semiconductor substrate 10. Further, a trenched gate 14 made of polysilicon is then formed within the trench.
Then, as shown in FIG. 1B, ion implantation is performed to dope N-type impurities or dopants to form an N-type doping region 16 while a photoresist pattern 15 is used as the implanting mask. Referring to FIG. 1C, the photoresist pattern 15 is removed followed by the deposition of an insulating layer 18.
Next, as shown in FIG. 1D, a photoresist pattern 20 having an opening 22 is formed on the insulating layer 18. An anisotropic etching step creates a source contact window 22, thereby leaving an insulator structure 18a under the photoresist pattern 15. Further, ion implantation is performed to dope P-type impurities within the N-type doping region 16 so as to form a P-type doping region 24.
As shown in FIG. 1E, a thermal re-flowing step is used to treat the insulator structure 18a to form insulator structure 18b having a rounded surface. An aluminum layer (not shown) is sputtered on the insulating layer 18b to contact the source contact window 22.
However, the method of fabricating a DMOS transistor described above involves complex processing and high costs (such as photolithography and re-flowing). Moreover, the thermal re-flowing step as illustrated in FIG. 1E can cause undesirable change in the doping region thus altering the performance of the DMOS transistor. Furthermore, high thermal budget is required in the thermal re-flowing step.
Embodiment of the present invention are directed to improving the performance of a DMOS transistor. One feature of the invention is to provide a method of fabricating a DMOS transistor to reduce processing complexity by eliminating at least one photolithography process. Another feature of the invention to provide a method of fabricating a DMOS transistor to reduce the thermal budget by using wet etching to replace thermal re-flowing.
In accordance with an aspect of the present invention, a method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate; implanting first conductive dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form a first doping region; depositing an insulating layer over the semiconductor substrate; and selectively etching the insulating layer to form a source contact window over a central portion of the first doping region and to leave an insulator structure above the trenched gate. The source contact window of the insulating layer has an enlarged top portion which is larger in size than a bottom portion of the source contact window closer to the first doping region than the enlarged top portion. Second conductive dopants are implanted through the source contact window to form a second doping region in the central portion of the first doping region.
In some embodiments, a wet etching is performed after implanting the second conductive dopants to reshape the insulator structure to form a rounded surface above the trenched gate. Selectively etching the insulating layer may comprise forming a photoresist pattern having an opening on the insulating layer above the first doping region, and dry etching the insulating layer through the opening to form the source contact window having the enlarged top portion over the central portion of the first doping region and to leave the insulator structure above the trenched gate. A conductive layer on the insulator structure may be formed, after implanting the second conductive dopants, to contact the source contact window. The conductive layer may be made of aluminum or an aluminum alloy. The first insulating layer may comprise BPSG or silicon oxide.
In some embodiments, the first conductive dopants are N-type dopants, and the second conductive dopants are P-type dopants. In other embodiments, the first conductive dopants are P-type dopants, and the second conductive dopants are N-type dopants. A junction depth of the first doping region is shallower than a junction depth of the second doping region. The method may further comprise removing a portion of the first doping region and the second doping region from the surface of the semiconductor substrate, wherein the first doping region has a concentration of the first conductive dopants which is larger than a maximum concentration of the second conductive dopants in the second doping region.
In accordance with another aspect of the present invention, a method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate; implanting N-type dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form an N-type doping region; depositing an insulating layer over the semiconductor substrate; forming a photoresist pattern having an opening above a central portion of the N-type doping region; wet etching the insulating layer through the opening of the photoresist pattern to form an undercut structure in the insulating layer below the opening of the photoresist pattern; and dry etching the insulating layer through the opening of the photoresist pattern to form a source contact window over the central portion of the N-type doping region and to leave an insulator structure under the photoresist pattern and above the trenched gate. The source contact window of the insulating layer has an enlarged top portion formed by the undercut structure. The method further comprises implanting P-type dopants through the source contact window to form a P-type doping region in the central portion of the N-type doping region; and removing the photoresist pattern.
In some embodiments, a wet etching is performed after removing the photoresist pattern to reshape the insulator structure to form a rounded surface above the trenched gate. A junction depth of the N-type doping region is shallower than a junction depth of the P-type doping region. Wet etching of the insulating layer is performed by buffered oxide etchant (BOE) or hydrogen fluoride (HF). Dry etching of the insulating layer is performed by reactive ion etching (RIE).